1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly to a semiconductor memory device provided with a stacked gate including a charge accumulation layer and a control gate.
2. Description of the Related Art
Conventionally, there is known a NAND type EEPROM (Electrically Erasable and Programmable Read Only Memory) as a nonvolatile semiconductor memory. In the NAND type EEPROM, plural memory cell transistors whose current paths are connected in series to form a memory cell unit (hereinafter, referred to as a NAND string). Recently, the number of word lines included in one NAND string tends to be increased due to the growing demands for higher levels of integration.
The word line is drawn to the outside of a memory cell array and connected to a row decoder through a contact plug. At this point, the word line is processed such that a width of the word line attains a minimum processing dimension F. For example, Jpn. Pat. Appln. KOKAI Publication No. 2002-151601 proposes a layout in which misalignment in photolithography is taken into account to prevent breaking or short-circuit of the word line or contact plug.
However, in the configuration disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2002-151601, an area of a contact plug forming region where the word line and the row decoder are connected is increased because the misalignment is taken into account. Therefore, a chip area tends to be increased.